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rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. dac8043 12-bit serial input multiplying cmos d/a converter features 12-bit accuracy in an 8-lead pdip package fast serial data input double data buffers low 1/2 lsb max inl and dnl max gain error: 1 lsb low 5 ppm/ c max tempco esd resistant low cost available in die form applications autocalibration systems process control and industrial automation programmable amplifiers and attenuators digitally controlled filters functional block diagram general description the dac8043 is a high accuracy 12-bit cmos multiplying dac in a space-saving 8-lead pdip package. featuring serial data input, double buffering, and excellent analog performance, the dac8043 is ideal for applications where pc board space is at a premium. in addition, improved linearity and gain error perfor- mance permit reduced parts count through the elimination of trimming components. separate input clock and load dac control lines allow full user control of data loading and analog output. the circuit consists of a 12-bit serial-in, parallel-out shift regis ter, a 12-bit dac register, a 12-bit cmos dac, and control logic. serial data is clocked into the input register on the rising edge of the clock pulse. when the new data word has been clocked in, it is loaded into the dac register with the ld input pin. data in the dac register is converted to an output current by the d/a converter. the dac8043? fast interface timing may reduce timing design considerations while minimizing microprocessor wait states. for applications requiring an asynchronous clear function or more versatile microprocessor interface logic, refer to the pm-7543. operating from a single 5 v power supply, the dac8043 is the ideal low power, small size, high performance solution to many application problems. it is available in a pdip pack age that is compatible with auto-insertion equipment. pin connections 8-lead pdip
rev. d ? dac8043?pecifications electrical characteristics (@ v dd = +5 v; v ref = +10 v; i out = gnd = 0 v; t a = full temperature range specified under absolute maximum ratings, unless otherwise noted.) dac8043 parameter symbol conditions min typ max unit static accuracy resolution n 12 bits nonlinearity 1 inl dac8043g ?/2 lsb dac8043f 1 lsb differential nonlinearity 2 dnl dac8043f/g ? lsb gain error 3 g fse t a = 25? dac8043f/g 2 lsb t a = full temperature range all grades 2 lsb gain tempco ( ? g ain/ ? temp) 4 tc gfs ? ppm/? power supply rejection ratio psrr ? v dd = ?% ?.0006 ?.002 %/% ( ? g ain/ ? v dd ) output leakage current 5 i lkg t a = 25? ? na t a = full temperature range dac8043f/g ?5 na zero scale error 6, 7 i zse t a = 25? 0.03 lsb t a = full temperature range dac8043f/g 0.15 lsb input resistance 8 r in 71115k ? ac performance output current settling time 4, 9 t s t a = 25? 0.25 1 s v ref = 0 v digital to analog i out load = 100 ? glitch energy 4, 10 qc ext = 13 pf 2 20 nvs dac register loaded alternately with all 0s and all 1s feedthrough error v ref = 20 v p-p @ f = 10 khz (v ref to i out ) 4, 11 ft digital input = 0000 0000 0000 0.7 1 mv p-p t a = 25? total harmonic distortion 4 thd v ref = 6 v rms @ 1 khz ?5 db dac register loaded with all 1s output noise voltage density 4, 12 e n 10 hz to 100 khz between r fb and i out 17 nv/ hz digital inputs digital input high v in 2.4 v digital input low v il 0.8 v input leakage current 13 i il v in = 0 v to +5 v 1 a input capacitance 4, 11 c in v in = 0 v 8 pf analog outputs output capacitance 4 c out digital inputs = v ih 110 pf digital inputs = v il 80 pf
rev. d dac8043 ? electrical characteristics (continued) dac8043 parameter symbol conditions min typ max unit timing characteristics 4, 14 data setup time t ds t a = full temperature range 40 ns data hold time t dh t a = full temperature range 80 ns clock pulsewidth high t ch t a = full temperature range 90 ns clock pulsewidth low t cl t a = full temperature range 120 ns load pulsewidth t ld t a = full temperature range 120 ns lsb clock into input register to load dac register time t asb t a = full temperature range 0 ns power supply supply voltage v dd 4.75 5 5.25 v supply current i dd digital inputs = v ih or v il 500 ? max digital inputs = 0 v or v dd 100 ? max notes 1 1 ?/2 lsb = ?.012% of full scale. 1 2 all grades are monotonic to 12 bits over temperature. 1 3 using internal feedback resistor. 1 4 guaranteed by design and not tested. 1 5 applies to i out ; all digital inputs = 0 v. 1 6 v ref = 10 v; all digital inputs = 0 v. 1 7 calculated from worst-case r ref : i zse (in lsbs) = (r ref i lkg 4096)/v ref . 1 8 absolute temperature coefficient is less than 300 ppm/?. 1 9 i out load = 100 ? , c ext = 13 pf, digital input = 0 v to v dd or v dd to 0 v. extrapolated to 1/2 lsb; t s = propagation delay (t pd ) + 9 where = measured time constant of the final rc decay. 10 v ref = 0 v, all digital inputs = 0 v to v dd or v dd to 0 v. 11 all digit inputs = 0 v. 12 calculations from en = 4k trb where: k = boltzmann constant, j/?, r = resistance, ? , t = resistor temperature, ?, b = bandwidth, hz. 13 digital inputs are cmos gates; i in is typically 1 na at 25?. 14 tested at v in = 0 v or v dd . specifications subject to change without notice. w afer test limits (@ v dd = 5 v, v ref = 10 v; i out = gnd = 0 v, t a = 25 c.) dac8043gbc parameter symbol conditions limit unit static accuracy resolution n 12 bits min integral nonlinearity inl ? lsb max differential nonlinearity dnl ? lsb max gain error g fse using internal feedback resistor ? lsb max power supply rejection ratio psrr ? v dd = ?% ?.002 %/% max output leakage current (i out )i lkg digital inputs = v il ? na max reference input input resistance r in 7/15 k ? min/max digital inputs digital input high v ih 2.4 v min digital input low v il 0.8 v max input leakage current i il v in = 0 v to v dd ? ? max power supply supply current i dd digital inputs = v in or v il 500 ? max digital inputs = 0 v or v dd 100 ? max note electrical tests are performed at wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualifications through sample lot asse mbly and testing.
rev. d e4e dac8043 absolute maximum ratings 1 (t a = 25?c, unless otherwise noted.) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +8 v v ref to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v v rfb to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v digital input voltage range . . . . . . . . . e0.3 v to v dd + 0.3 v v iout to gnd . . . . . . . . . . . . . . . . . . . . e0.3 v to v dd + 0.3 v operating temperature range fp versions . . . . . . . . . . . . . . . . . . . . . . . . . e40?c to +85?c gp version . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0?c to 70?c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150?c storage temperature . . . . . . . . . . . . . . . . . . . e65?c to +150?c lead temperature (soldering, 60 sec) . . . . . . . . . . . . . 300?c package type ja 2 jc unit 8-lead pdip 96 37 ?c/w notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. only one absolute maxi- mum rating may be applied at any one time. 2 ja is specified for worst-case mounting conditions, i. e., ja is specified for device in socket for pdip package. caution 1. do not apply voltages higher than v dd or less than gnd potential on any terminal except v ref (pin 1) and r fb (pin 2). 2. the digital control inputs are zener-protected; however, permanent damage may occur on unprotected units from high energy electrostatic fields. keep units in conductive foam at all times until ready to use. 3. use proper antistatic handling procedures. 4. absolute maximum ratings apply to both packaged devices and dice. stresses above those listed under absolute maxi- mum ratings may cause permanent damage to the device. ordering guide * relative temperature package model accuracy range option dac8043fp 1 lsb e40?c to +85?c 8-lead pdip dac8043gp 1/2 lsb 0?c to +70?c 8-lead pdip * all commercial and industrial temperature range parts are available with burn-in. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the dac8043 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. d t ypical performance characteristicsedac8043 e5e tpc 1. gain vs. frequency (output amplifier: op42) tpc 4. linearity error vs. digital code tpc 7. dnl error vs. reference voltage tpc 2. total harmonic distortion vs. frequency (multiplying mode) tpc 5. linearity error vs. reference voltage tpc 3. supply current vs. logic input voltage ? s tpc 6. logic threshold voltage vs. supply voltage
rev. d e6e dac8043 parameter definitions integral nonlinearity (inl) this is the single most important dac specification. adi mea- sures inl as the maximum deviation of the analog output (from the ideal) from a straight line drawn between the end points. it is expressed as a percent of full-scale range or in terms of lsbs. refer to pmi 1988 data book section 11 for additional digital- to-analog converter definitions. interface logic information the dac8043 has been designed for ease of operation. the timing diagram illustrates the input register loading sequence. note that the most significant bit (msb) is loaded first. once the input register is full, the data is transferred to the dac register by taking ld momentarily low. digital section the dac8043?s digital inputs, sri, ld, and clk, are ttl compatible. the input voltage levels affect the amount of cur- rent drawn from the supply; peak supply current occurs as the digital input (v in ) passes through the transition region (see tpc 3). maintaining the digital input voltage levels as close as possible to the supplies, v dd and gnd, minimizes supply cur- rent consumption. the dac8043?s digital inputs have been designed with esd resistance incorporated through careful layout and the inclusion of input protection circuitry. figure 1 shows the input protec tion diodes and series resistor; this input structure is duplicated on each digital input. high voltage static charges applied to the inputs are shunted to the supply and ground rails through forward biased diodes. these protection diodes were designed to clamp the inputs to well below dangerous levels during static discharge conditions. general circuit information the dac8043 is a 12-bit multiplying d/a converter with a very low temperature coefficient. it contains an r-2r resistor ladder network, data input, control logic, and two data registers. figure 1. digital input protection the digital circuitry forms an interface in which serial data can be loaded under microprocessor control into a 12-bit shift register and then transferred, in parallel, to the 12-bit dac register. a simplified circuit of the dac8043 is shown in figure 3, which has an inverted r-2r ladder network consisting of silicon-chrome, highly stable (50 ppm/?c) thin-film resistors, and twelve pairs of nmos current-steering switches. these switches steer binarily weighted currents into either i out or gnd; this yields a constant current in each ladder leg, regard less of digital input code. this constant current results in a constant input resistance at v ref equal to r. the v ref input may be driven by any reference voltage or current, ac or dc, that is within the limits stated in the absolute maximum ratings. the twelve output current-steering nmos fet switches are in series with each r-2r resistor; they can introduce bit errors if all are of the same r on resistance value. they were designed so that the switch on resistance is binarily scaled so that the voltage drop across each switch remains constant. if, for example, switch 1 of figure 3 were designed with an on resistance of 10 ? ?
rev. d dac8043 e7e dynamic performance output impedance the dac8043?s output resistance, as in the case of the output capacitance, varies with the digital input code. this resistance, looking back into the i out terminal, may be between 10 k ? ( ) ? ( ? ) vv r r error os fb o =+ ? ? ? ? ? ? 1 where r o is a function of the digital code and r o = 10 k ? r o = 30 k ? vv k k v error1 os os =+ ? ? ? ? ? ? = 1 10 10 2 ? ? vv k k v error2 os os =+ ? ? ? ? ? ? = 1 10 30 43 ? ? v os . since one lsb has a weight (for v ref = 10 v) of 2.4 mv for the dac8043, it is clearly important that v os be minimized, either by using the amplifier?s nulling pins or an external nulling network or by selecting an amplifier with inherently low v os . amplifiers with sufficiently low v os include adi?s op77, op07, op27, and op42. figure 5. simplified circuit to further ensure accuracy across the full temperature range, permanently on mos switches were included in series with the feedback resistor and the r-2r ladder?s terminating resistor. the simplified dac circuit, figure 3, shows the location of the series switches. these series switches are equivalently scaled to two times switch 1 (msb) and to switch 12 (lsb) , respec tively, to maintain constant relative voltage drops with varying tempera- ture. during any testing of the resistor ladder or r feedback (such as incoming inspection), v dd must be present to turn on these series switches. figure 3. simplified dac circuit equivalent circuit analysis figure 4 shows an equivalent analog circuit for the dac8043. the (d )
rev. d e8e dac8043 figure 7. unipolar operation with fast op amp and gain error trimming (2-quadrant) g ain error may be trimmed by adjusting r 1 , as shown in figure 7. the dac register must first be loaded with all 1s. r 1 may then be adjusted until v out = ev ref (4095/4096). in the case of an adjustable v ref , r 1 and r 2 may be omitted, with v ref ad justed to yield the desired full-scale output. in most applications, the dac8043?s negligible zero-scale error and very low gain error permit the elimination of the trimming components (r 1 and the external r 2 ) without adversely affecting on circuit performance. the gain and phase stability of the output amplifier, board layout, and power supply decoupling all affect the dynamic performance. the use of a small compensation capacitor may be required when high speed operational amplifiers are used. it may be connected across the amplifier?s feedback resistor to provide the necessary phase compensation to critically damp the output. the dac8043?s output capacitance and the r fb resistor form a pole that must be outside the amplifier?s unity gain crossover frequency. the considerations when using high speed amplifiers are: 1. phase compensation (see figures 6 and 7). 2. power supply decoupling at the device socket and the use of proper grounding techniques. applications information application tips in most applications, linearity depends upon the potential of i out and gnd (pins 3 and 4) being equal to each other. in most applications, the dac is connected to an external op amp with its noninverting input tied to ground (see figures 6 and 7). the amplifier selected should have a low input bias current and low drift over temperature. the amplifier?s input offset voltage should be nulled to less than 200 v (less than 10% of 1 lsb). the operational amplifier?s noninverting input should have a minimum resistance connection to ground; the usual bias current compensation resistor should not be used. this resistor can cause a variable offset voltage appearing as a varying output error. all grounded pins should tie to a single common ground point, avoid- ing ground loops. the v dd power supply should have a low noise level with no transients greater than 17 v. unipolar operation (2-quadrant) the circuit shown in figures 6 and 7 may be used with an ac or dc reference voltage. the circuit?s output will range between 0 v and approximately ev ref (4095/4096), depending upon the digital input code. the relationship between the digital input and the analog output is shown in table i. the limiting parameters for the v ref range are the maximum input voltage range of the op amp or 25 v, whichever is lowest. figure 6. unipolar operation with high accuracy op amp (2-quadrant) table i. unipolar code table digital input nominal analog output msb lsb (v out as shown in figures 6 and 7) 1111 1111 1111 ? ? ? ? ? ? ? v ref 4095 4096 1000 0000 0001 ? ? ? ? ? ? ? v ref 2049 4096 1000 0000 0000 ? ? ? ? ? ? ? =? v v ref ref 2048 4096 2 0111 1111 1111 ? ? ? ? ? ? ? v ref 2047 4096 0000 0000 0001 ? ? ? ? ? ? ? v ref 1 4096 0000 0000 0000 ? ? ? ? ? ? ? = v ref 0 4096 0 notes 1. nominal full scale for figures 6 and 7 circuits is given by fs v ref =? ? ? ? ? ? ? lsb v or v ref ref n = ? ? ? ? ? ? () ?
rev. d dac8043 e9e table ii. bipolar (offset binary) code table digital input nominal analog output msb lsb (v out as shown in figure 8) 1111 1111 1111 + ? ? ? ? ? ? v ref 2047 2048 1000 0000 0001 + ? ? ? ? ? ? v ref 1 2048 1000 0000 0000 0 0111 1111 1111 ? ? ? ? ? ? ? v ref 1 2048 0000 0000 0001 ? ? ? ? ? ? ? v ref 2047 2048 0000 0000 0000 ? ? ? ? ? ? ? v ref 2048 2048 notes 1. nominal full scale for figure 8 circuit is given by fs v ref = ? ? ? ? ? ? lsb v ref = ? ? ? ? ? ? ( ) = = vv aa a a oin =? +++ ? ? ? ? ? ? v v aa a a o in = ? +++ ? ? ? ? ? ? ? ? ? ? ( ) ( ) ( ) ()
rev. d e10e dac8043 figure 9. analog/digital divider interfacing to the mc6800 as shown in figure 10, the dac8043 may be interfaced to the 6800 by successively executing memory write instructions while manipulating the data between writes, so that each write presents the next bit. in this example the most significant bits are found in memory location 0000 and 0001. the four msbs are found in the lower half of 0000, the eight lsbs in 0001. the data is taken from the db 7 line. the serial data loading is triggered by the clk pulse, which is asserted by a decoded memory write to memory location 2000, r/ w , and
rev. d dac8043 e11e outline dimensions 8-lead plastic dual in-line package [pdip] (n-8) dimensions shown in inches and (millimeters) seating plane 0.015 (0.38) min 0.180 (4.57) max 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) 8 1 4 5 0.295 (7.49) 0.285 (7.24) 0.275 (6.98) 0.100 (2.54) bsc 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-095aa
rev. d c00271e0e3/03(d) e12e dac8043 revision history location page 3/03?data sheet changed from rev. c to rev. d. deleted 8-lead cirdip and 16-lead wide-body sol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal figures renumbered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 deleted to dice characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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